| Аннотація | Сontex. The programmable logic integrated circuits FPGA (field-programmable gate array) used realization of the generator of functions LUT (Look Up Table), which is configured by loading a configuration memory for calculating a logic function in perfectdisjunctive normal form (PDNF). The LUT dimension determines the technological limitations of Mead and Conway on the number of series-connected MOS transistors. The standard number of LUT inputs for many years was 3 or 4, and 4-LUT is constructed from two 3-LUTs with an additional 1-LUT. However, in many projects, it is required to calculate functions of a large number of arguments. This requires a multi-input LUT, which is built as a decomposition of 3-LUT, 4-LUT. The speed of computing logic functions determines by the delay in the coupling matrices, so this decomposition leads to a decrease in performance. In recent years, the direction of adaptive logical modules (ALM) has been actively developing, in which the user has access to various versions o |